Many integrated circuit chips have multiple voltage domains, i.e., the circuit operates with different power supply voltages. When a digital circuit is powered up, it is usually reset to establish a predetermined state (i.e., initial digital values are populated in registers, memory, etc.). For chips containing multiple voltage domains, some existing POR techniques only detect the ramp-up of the power supply that occurs last in time. Until this time, however, the state of the POR signal or signals is undetermined, which may lead to malfunctioning of the chip, such as contention in tri-state logic circuits and/or malfunctioning of memory circuits. Both of these conditions can lead to excessive and undesirable current consumption. Moreover, conventional POR techniques for multi-voltage circuits are sequence-dependent because they only monitor for ramp-up of the last power supply voltage signal. Since the ramp-up sequences of such circuits are predefined, a random power-up sequence may lead to system failure.
Accordingly, it is desirable to have a sequence-independent POR methodology and related circuit for use in a multi-voltage architecture. In addition, it is desirable to have a POR methodology and related circuit that minimizes steady state and dynamic current consumption associated with the generation of POR signals. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.